//CWE-1271 Consider the example Locked_override_register example. 
/*
Shown below is a positive clock edge triggered flip-flop used to implement a lock bit 
for test and debug interface. When the circuit is first brought out of reset, 
the state of the flip-flop will be unknown until the enable input and D-input signals update the flip-flop state. 
In this example, an attacker can reset the device until the test and debug interface is unlocked 
and access the test interface until the lock signal is driven to a known state by the logic.
*/
module lock_on_reset (
    input wire clk, resetn, unlock, d,
    output reg locked);
always @(posedge clk or negedge resetn)begin
    if(unlock) locked <= d;
    else locked <= locked;
    // if(~resetn) locked <=0;
    // else if(unlock) locked <= d;
    // else locked <=locked;
end
always @(posedge clk)begin
    if($fell(resetn) || ($past(~resetn)&&(~resetn)))begin
        assert(locked==0);
    end
end
endmodule